The present invention relates to a capacitor and a method of forming the same, and more particularly to a capacitor in a semiconductor memory device and a method of forming the same.
A ferroelectric memory has a capacitor utilizing a semiconductor in combination with a ferroelectric, for example, Pb(Zr.sub.1-x, Ti.sub.x)O.sub.3 hereinafter referred to as a "PZT", wherein a remanence of the ferroelectric is utilized to store "1" and "0". FIG. 1 is a diagram illustrative of a variation in polarization of the ferroelectric versus an applied bias to the ferroelectric of the ferroelectric capacitor. Once a positive bias is applied to the ferroelectric, then the bias becomes zero, whereby the polarization does not become zero and a positive remanence Pr remains. Once a negative bias is applied to the ferroelectric, then the bias becomes zero, whereby the polarization does not become zero and a negative remanence -Pr remains. The positive and negative remanences are detected to judge "1" and "0" as binary digit data. After a power is discontinued, the informations of "1" and "0" remain, for which reason a non-volatile memory can be realized. In this memory, the ferroelectric capacitor and a silicon LSI are formed on the same substrate, wherein both the ferroelectric capacitor and the silicon LSI are required to show sufficiently high performances. In the manufacturing processes, the capacitor is covered by a barrier layer such as a silicon nitride barrier layer to prevent a reduction of the ferroelectric in a hydrogen atmosphere for the silicon LIS process after the ferroelectric capacitor is shaped by a dry etching. Particularly, a hydrogen anneal process is important for reducing the interface state density of the MOS transistors after aluminum interconnections have been formed.
In Japanese patent applications Nos. 7-111318 and 9-049526, the ferroelectric capacitors and methods of forming the same are disclosed. FIGS. 2A through 2M are fragmentary cross sectional elevation views illustrative of a conventional method of forming ferroelectric capacitors in a semiconductor memory device.
With reference to FIG. 2A, a bottom electrode layer 2 comprising laminations of a Pt layer and a Ti layer is laminated on a BPSG base oxide layer 1. A PZT ferroelectric layer 3 is laminated on the bottom electrode layer 2. A Pt top electrode layer 4 is laminated on the PZT ferroelectric layer 3.
With reference to FIG. 2B, a first photo-resist pattern 6 is selectively formed on the Pt top electrode layer 4.
With reference to FIG. 2C, a first dry etching is carried out by use of the first photo-resist pattern 6 to selectively etch the laminations of the PZT ferroelectric layer 3 and the Pt top electrode layer 4. As a reaction gas, a mixture gas of a Cl.sub.2 and Ar is used to selectively etch the Pt top electrode layer 4. As a reaction gas, a mixture gas of a CF.sub.4 and Ar is used to selectively etch the PZT ferroelectric layer 3, whereby the top electrode is formed.
With reference to FIG. 2D, the used first photo-resist pattern 6 is removed.
With reference to FIG. 2E, a second photo-resist pattern 8 is formed which covers the top electrode comprising the PZT ferroelectric layer 3 and the Pt top electrode layer 4 and also covers a peripheral region of the top electrode.
With reference to FIG. 2F, a second dry etching is carried out by use of the second photo-resist pattern 8 to selectively etch the bottom electrode layer 2. As a reaction gas, a mixture gas of a Cl.sub.2 and Ar is used to selectively etch the bottom electrode layer 2. The bottom electrode is formed.
With reference to FIG. 2G, the second photo-resist pattern 8 is removed, whereby the ferroelectric capacitor is shaped on the base layer 1.
With reference to FIG. 2H, a silicon nitride hydrogen barrier layer 12 is entirely deposited to cover the ferroelectric capacitor.
With reference to FIG. 2I, a third photo-resist pattern 9 is formed on the silicon nitride hydrogen barrier layer 12.
With reference to FIG. 2J, a third dry etching is carried out by use of the third photo-resist pattern 9 to form an opening in the silicon nitride hydrogen barrier layer 12, so that the opening is positioned over the top electrode 4 of the ferroelectric capacitor.
With reference to FIG. 2K, the third photo-resist pattern 9 is removed.
With reference to FIG. 2L, a heat treatment is carried out in an oxygen atmosphere to recover the damage of the PZT ferroelectric layer 3, wherein the PZT ferroelectric layer 3 has received the damage in the process of forming the silicon nitride hydrogen barrier layer 12.
With reference to FIG. 2M, a capacitor cover layer 10 is entirely formed which covers the top of the top electrode 4 of the ferroelectric capacitor and the silicon nitride hydrogen barrier layer 12.
In the above processes, after the top electrode and the bottom electrode are formed by the dry etchings using the photo-resist patterns as masks, the hydrogen barrier layer is entirely formed.
After the capacitor cover layer 10 has been formed, aluminum interconnection layers are formed and a hydrogen anneal is carried out.
The above conventional processes have the following problems. The photo-resist films are used as the masks for dry etching processes to form the top and bottom electrodes. The use of the photo-resist is advantageous in convenience but the following problems are raised.
The first problem is in shapes of the PZT ferroelectric layer 3 and the Pt top electrode 4. FIG. 3A is an enlarged fragmentary cross sectional elevation view illustrative of the edge of the ferroelectric capacitor in a dry etching process of FIG. 2C. FIG. 3B is an enlarged fragmentary cross sectional elevation view illustrative of the edge of the ferroelectric capacitor after aching process for removal of a used photo-resist pattern of FIG. 2D. As shown in FIG. 3A, a side wall deposit 13 is deposited on side walls of the laminations of the PZT ferroelectric layer 3, the Pt top electrode 4 and the first photo-resist pattern 6. Reaction products of Pt and PZT are non-volatile and are deposited on the side walls hereby forming the side wall deposit 13. A selective etching rate of Pt or PZT to the photo-resist is 1:2. The necessary thickness of the photo-resist is about 2 micrometers, so that the photo-resist film has a thickness of not less than about 1 micrometer after the dry etching has been carried out in order to obtain a sufficiently high accuracy in patterning the top electrode. The height of the side wall deposit 13 is almost the same as the height of the photo-resist film. After the first photo-resist film 6 has been removed, the side wall deposit 13 remains as shown in FIG. 3B. If the side wall deposit 13 is made into contact with the top electrode 4, a short circuit is formed between the top and bottom electrodes. The formation of the side wall deposit 13 reduces the yield of the semiconductor device having the capacitor.
In order to suppress the formation of the side wall deposit 13, it is most effective to retreat the photo-resist film during the dry etching process. FIG. 4A is an enlarged fragmentary cross sectional elevation view illustrative of the edge of the ferroelectric capacitor in a dry etching process of FIG. 2C. FIG. 4B is an enlarged fragmentary cross sectional elevation view illustrative of the edge of the ferroelectric capacitor after aching process for removal of a used photo-resist pattern of FIG. 2D. In order to retreat the photo-resist film during the dry etching process, a reactive gas including a large amount of a gas such as Cl.sub.2 having a low selective ratio to the photo-resist is used so that the photo-resist is etched in a lateral direction. The cross sectional shape of the photo-resist becomes tapered shape so that the side walls are gently sloped whereby the side wall deposit is unlikely to be formed in the dry etching process. Once the side wall deposit is formed on the gently sloped side walls, then the side wall deposit is likely to be etched by the dry etching process. The Pt top electrode layer 4 may be etched to form gently sloped side walls and the cross sectional shape of the Pt top electrode layer 4 becomes tapered. Generally, the thickness of the Pt top electrode layer is about 200 nanometers. The thickness of the Pt layer of the bottom electrode layer is also about 200 nanometers. The thickness of the Ti layer of the bottom electrode layer is about 20 nanometers. The thickness of the PZT ferroelectric layer is about 300 nanometers. If the tapered angle or the grade of the gentle slop of the side wall becomes not more than 45 degrees, the horizontal size of the top electrode is different from the designed value. For example, if the top size of the top electrode is 1 micrometer, then the bottom size of the bottom electrode is 2 micrometers. This makes it difficult to scale down the horizontal size of the capacitor and also to improve the density of integration of the semiconductor device.
The use of the photo-resist mask for the drying etching processes for etching the Pt top electrode layer and the PZT ferroelectric layer makes it difficult to obtain a highly accurate horizontal size of the top electrode of the ferroelectric capacitor
In the above circumstances, it had been required to develop a novel capacitor and a novel method of forming the capacitor free from the above problem.